The present invention relates to a semiconductor device, and in particular, to a semiconductor device having an electric circuit in which two or more FETs (Field-Effect Transistors) are desired to have equal characteristics.
With the progress of information communication devices in recent years, research and development has been undertaken for increasing the packing density and capacity of semiconductor devices such DRAMS (Dynamic Random Access Memory). In the circuit layout design of DRAM etc., a necessary electric circuit is placed in an area allocated on a Si (silicon) substrate under certain design rules (dimensional restrictions such as minimum processing dimensions). Each element or component (FET etc.) of the electric circuit is electrically isolated from other elements by use of a structure called “shallow trench isolation” (STI), in which a shallow trench is formed on the Si substrate and the trench is filled with silicon oxide etc. for electrical insulation.
As methods for forming element isolation parts (fields) and areas, a method forming trenches and filling them with insulating material, a method forming thermally-oxidized films, etc. have been disclosed in JP-A-1-223741, JP-A-4-42948, JP-A-8-241922, JP-A-8-279553, etc.
In the conventional circuit layout design, however, electrical characteristics concerning the shallow trench isolation have been regarded as those for merely isolating and separating adjacent elements (FET etc.). Therefore, other characteristics such as the width of the trench have not been taken into consideration for the transistor characteristics. The trench width of the shallow trench isolation that is formed adjacent to an element (hereafter, also referred to as “STI trench width”), which is in many cases determined by surrounding circuit layout, used to vary depending on the case, and there used to be cases where two FETs that are desired to have equal characteristics had different STI trench widths.
In memory devices such as DRAM, information stored in each memory cell is read out by a sense amplifier circuit by detecting the change of voltage on a bit line. Since the voltage change on the bit line is extremely small, the sense amplifier circuit generally employs two transistors having equal characteristics to be capable of detecting the subtle voltage difference on the bit line. As mentioned above, the shallow trench isolation has been regarded merely as a means for isolating and separating each element such as FET, and as a result, two transistors that are desired to have equal characteristics in circuit layout of a sense amplifier circuit used to have different STI trench widths. However, even in such a circuit layout designing method, no characteristics difference occurred between the two transistors that are desired to have equal characteristics.
In DRAM whose storage capacity is increasing constantly, miniaturization and high integration are being promoted in its sense amplifier circuit as well as in its memory section. In conventional circuit layout designing methods, the miniaturization of the sense amplifier circuit is basically carried out by simply scaling down the circuit layout of previous-generation sense amplifier circuit having larger processing dimensions, therefore, the difference in the STI trench width tended to be maintained. Meanwhile, by the micromachining technology of recent years, the STI trench width has become as narrow as approximately 0.2 μm at its narrowest part.
As explained above, the conventional circuit layout design for increasing the capacity and integration of a semiconductor device is conducted basically by scaling down the previous-generation circuit layout having larger processing dimensions. The shallow trench isolation in the conventional circuit layout is used for the purpose of simply isolating and separating the elements, and thus there are cases where the width of the shallow trench isolation adjacent to the FET varies among FETs that are required to have equal characteristics. Meanwhile, as a result of the device miniaturization of recent years, the narrowest part of the shallow trench isolation has become as narrow as approximately 0.2 μm and is expected to be still narrower in the future.
The present inventors found out that the conventional scaling down of circuit layout might cause characteristics difference between the FETs that are desired to have equal characteristics.
The shallow trench isolation, which is obtained by forming a shallow trench on a Si substrate and filling the trench with silicon oxide, is known as a source of stress. Specifically, the stress grows in active areas around the shallow trench isolation during an oxidation process after the formation of the shallow trench on the Si substrate. The present inventors made it clear by stress analysis that the stress growing in the active around the trench increases rapidly as the STI trench width gets narrower than 1 μm.
The shallow trench isolation, which is obtained by forming a shallow trench on a Si substrate and filling the trench with silicon oxide, is known as a source of stress. Specifically, the stress grows in active areas around the shallow trench isolation during an oxidation process after the formation of the shallow trench on the Si substrate. The present inventors made it clear by stress analysis that the stress growing in the active around the trench increases rapidly as the STI trench width gets narrower than 1 μm.